1. Field of Invention
The present invention relates to signal detection and in particular an integrated circuit signal detector for a data communication system.
2. Description of Related Art
The detection of signals at a specific frequency with a specific signal strength is often required in a data communication system. As an example, in an Ethernet system certain signals with an amplitude greater than 200 mv are required to be detected before a link between two stations can be established. It is desirable to have this detection capability implemented in an integrated circuit using typical digital circuit process steps.
In U.S. Pat. No. 5,940,400 (Eastmond et al.) a method and device is directed to provide collision presence detection in wireless intensity modulated binary coded transceivers. A measurement of the degree of correlation which exists between a transmitted signal and a received signal provides the basis for collision detection. In U.S. Pat. No. 5,717,720 (Jackson et al.) is directed to digital data receivers, methods and circuitry for differentiating between signals and data packets of varying protocols and frequencies transferred over a digital burst mode communications system. U.S. Pat. No. 5,199,049 (Wilson) is directed to a digital squelch circuit for detecting valid data signals in a burst mode communication system, e.g. a packet based LAN. A counter is started in a squelch circuit and input signals are detected at various interval of the counter. If there is an input signal transition a predetermined number of times as measured by the counter, the input signal is defined as valid.
A typical implementation of a signal detector is shown in FIG. 1. A differential input 10 is connected to a high pass filter 11. The high pass filter 11 comprising circuit elements C1, C2, R1 and R2 is connected to a first operational amplifier 12 connected in differential mode. The output of the first operational amplifier 12 is connected to a low pass filter 13 comprising circuit elements C3, C4, R3 and R4. The low pass filter 13 is further connected to a second operational amplifier 14 connected in differential mode. In the output circuitry of the second operational amplifier 14 is an offset circuit 15 comprising resistors R5 and R6 and current sources J1 and J2. The offset is determined by the current from current source J2 flowing through R6. A comparator 16 is connected to the offset circuitry 15 such that a signal from second operational amplifier 14 must be larger than the offset voltage to produce a signal at the output 17 of the comparator 16.
If the cutoff frequency of the high pass filter 11 is lower than the cutoff frequency of the low pass filter 13, then a signal at the differential input 10 with a frequency between the two cut off frequencies will produce an output from the second operational amplifier 14. If the input signal has sufficient amplitude to overcome the offset voltage produced by the offset circuitry 15, then the comparator will produce a pulse at the output 17.
A problem with the circuitry of FIG. 1 is that it is difficult to integrate the circuitry into a chip containing digital circuitry. Capacitors C1 and C2 are connected in a "floating" configuration where they are not directly connected to ground or a circuit bias. Using a CMOS integrated circuit processes it is not easy to implement these capacitors. Either special silicon wafer steps are required that are not a part of typical CMOS digital circuit process steps, or a big area is required to facilitate a metal layer to metal layer capacitors. A second problem results from the need for multiple stages requiring relatively complicated circuitry in each stage which increases the cost of design and manufacture but also has a tendency to limit the circuit performance at high frequency signals.